| 摘要 |
A system controller (SC0, SC1) executes, based on states of cache memories of CPUs managed by the system controller and states of resources for data transfer, snoop processing for selecting "BUSY", "HIT", "HIT & BUSY", "MISS & BUSY", or "MISS" as a status for each of the cache memories with respect to data requested by a fetch request, which is a memory access request issued by a CPU 1a and notifies the other system controller (SC0, SC1) of a snoop processing result. The system controller (SC0, SC1) sets priority of statuses as "BUSY", "HIT", "HIT & BUSY", "MISS & BUSY", and "MISS" in order from "BUSY" having highest priority, merges all the statues, and determines a final status. The system controller (SC0, SC1) retries, when the final status is "BUSY", "HIT & BUSY", or "MISS & BUSY", the snoop processing and starts, when the final status is "HIT" or "MISS", memory access processing for executing data transfer corresponding to the final status. |
