| 摘要 |
A process management method for managing manufacturing variability of an interconnection included in a semiconductor device is provided. The process management method includes: calculating interconnect resistance and interconnect capacitance regarding an interconnection included in the semiconductor device, under a condition that manufacturing variability of a width and a thickness of the interconnection is expressed by points on a predetermined circle of equal probability of a joint probability density function; and defining, based on the calculated interconnect resistance and interconnect capacitance, a variation range of interconnect resistance and interconnect capacitance caused by manufacturing variability. The variation range is defined two-dimensionally in a coordinate system where a first axis represents interconnect resistance and a second axis represents interconnect capacitance.
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