发明名称 DECODER AND CODER
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a decoder capable of reducing transfer band width to reduce cost. <P>SOLUTION: The decoder is provided with n (n is an integer≥2)submodules SM1-SMn which perform deblocking filter processing to a decoded image per macro block, wherein each submodule includes: a current macro block input memory; an upper macro block pixel intermediate data memory which stores pixel data at a lower boundary part of a macro block on a current macro block; a left macro block pixel intermediate data memory which stores pixel data of a right boundary part of a macro block at the left side of the current macro block; and a filter circuit which performs the deblocking filter processing, and a filter circuit of a k-th (k is an integer which satisfies 1≤k≤n-1) submodule stores pixel data of a pixel at a lower boundary part of the macro block after the deblocking filter processing in the upper macro block pixel intermediate data memory of a (k+1)-th submodule. <P>COPYRIGHT: (C)2010,JPO&INPIT</p>
申请公布号 JP2009278371(A) 申请公布日期 2009.11.26
申请号 JP20080127462 申请日期 2008.05.14
申请人 TOSHIBA CORP 发明人 NAKAYAMA HIROMITSU
分类号 H04N19/50;H04N19/423;H04N19/436;H04N19/44;H04N19/80;H04N19/86 主分类号 H04N19/50
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