| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor storage capable of speedily and precisely determining the information of a memory cell with low power consumption while avoiding read disturbance even in the memory cell where a voltage applicable between input and output terminals is restricted. <P>SOLUTION: The semiconductor storage has, a memory array 100 having memory cells M11-Mnm, a bit line charge and discharge circuit 102, a bit line selection circuit 103, and a load circuit 105 connected between a data line DL connected to the bit line selection circuit 103 and a sense amplifier 104. The load circuit 105 has a series resistor RL and a parallel capacitor CL connected to the data line DL in series. By the load circuit 105, a sufficient read margin can be secured while a voltage applied between the input and output terminals of the memory cell is kept low to prevent the read disturbance from occurring, thus enabling fast read with low power consumption. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
