Shallow junction formation

摘要

A method of forming junctions in a semiconductor substrate, where a gate dielectric layer is grown on the semiconductor substrate, a gate electrode layer is deposited on the gate dielectric layer, and a sacrificial layer is formed on the gate electrode layer. The sacrificial layer is patterned with a material to cover portions of the sacrificial layer and expose portions of the sacrificial layer. The exposed portions of the sacrificial layer are etched to remove the exposed portions of the sacrificial layer and expose portions of the gate electrode layer. The exposed portions of the gate electrode layer are etched to expose portions of the gate dielectric layer and form a gate electrode having exposed vertical faces. The sacrificial layer and the exposed portions of the gate dielectric layer are impregnated with a first species that inhibits diffusion of oxygen through the sacrificial layer and the exposed portions of the gate dielectric layer. The impregnation is accomplished using a process that does not impregnate a significant amount of the first species in the exposed vertical faces of the gate electrode. The impregnated sacrificial layer, the exposed vertical faces of the gate electrode, and the impregnated exposed portions of the gate dielectric layer are exposed to an oxidizing environment, causing oxide growth on at least the exposed vertical faces of the gate electrode, and thereby covering the vertical faces of the gate electrode with oxide sidewalls. However, the oxidizing environment does not cause significant oxide growth under the impregnated sacrificial layer and the impregnated exposed portions of the gate dielectric layer. A second species is impregnated through the impregnated exposed portions of the gate dielectric layer into portions of the semiconductor substrate that underlie the impregnated exposed portions of the gate dielectric layer. The impregnated second species forms junctions in the portions of the semiconductor substrate that underlie the impregnated exposed portions of the gate dielectric layer.