发明名称 PAD DESIGN FOR STT-MRAM
摘要 A pad with reduced capacitance loading for a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell array is provided. The pad includes a plurality of hollow-shaped lower metal layers and a planar top metal layer formed on an uppermost layer of the plurality of hollow-shaped lower metal layers.
申请公布号 CA2723830(A1) 申请公布日期 2009.11.26
申请号 CA20092723830 申请日期 2009.05.08
申请人 QUALCOMM INCORPORATED 发明人 XIA, WILLIAM;KANG, SEUNG H.
分类号 H01L23/528;H01L27/22 主分类号 H01L23/528
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