| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a counter, which reduces propagation time delay of the counter and minimizes data skew. Ž<P>SOLUTION: An n-bit counter includes n counter blocks each including: a D-flipflop; a second MUX which selects any one of external data and a second output signal of the D-flipflop in response to a data load signal and outputs a selected signal; and a first MUX which transfers any one of a first output signal of the D-flipflop and the output signal of the second MUX as an input signal of the D-flipflop in response to a counter enable signal or the data load signal. Here. an mth counter block outputs an mth bit signal, which is toggled in a period where all output signals of second MUXs included in first to (m-1)th counter blocks are at a first level and the counter enable signal is at a second level. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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