| 摘要 |
An acquisition unit of a GNSS receiver base band circuit comprises an integrator (27) with a number of preprocessors (29a-h) where an incoming digital signal is mixed with different frequency signals to compensate at least in part for clock drift and Doppler shifts. The resulting digital signals are in each case, after an accumulation step reducing sample frequency, integrated over an integration period extendinging over several, e.g., twenty, basic intervals of the length of a basic sequence characteristic for a GNSS satellite, usually 1 ms, in such a way that samples separated by a multiple of the basic interval are superposed. The resulting data sequence of 1,023 digital values is stored in one of two memories (34, 35) and then, in mixers (38, 39), sequentially shifted by post-integration frequencies which are multiples of the inverse of the length of the basic interval, usually 1 kHz, whereas the pre-integration frequencies employed in the preprocessors (29a-h) deviate, with one possible exception, from the said post-integration frequencies and are usually smaller, preferably multiples of the integration period, e.g., 50 Hz.
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