发明名称 |
Method and apparatus for efficient integer transform |
摘要 |
A method and apparatus for including in a processor instructions for performing integer transforms including multiply-add operations and horizontal-add operations on packed data. In one embodiment, a processor is coupled to a memory that stores a first packed byte data and a second packed byte data. The processor performs operations on said first packed byte data and said second packed byte data to generate a third packed data in response to receiving a multiply-add instruction. A plurality of the 16-bit data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed byte data. The processor adds together at least a first and a second 16-bit data element of the third packed data in response to receiving an horizontal-add instruction to generate a 16-bit result as one of a plurality of data elements of a fourth packed data.
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申请公布号 |
US7624138(B2) |
申请公布日期 |
2009.11.24 |
申请号 |
US20030749738 |
申请日期 |
2003.12.30 |
申请人 |
INTEL CORPORATION |
发明人 |
DEBES ERIC;MACY WILLIAM W.;TYLER JONATHAN J. |
分类号 |
G06F7/38;G06F9/30;G06F9/302;G06F9/308;G06F9/315;G06F9/38;G06F17/14 |
主分类号 |
G06F7/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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