发明名称 Memory device interface methods, apparatus, and systems
摘要 Apparatus and systems may include a substrate, an interface chip disposed on the substrate, a first memory die having a plurality of memory arrays disposed on the interface chip, the first memory die coupled to a plurality of through wafer interconnects (TWI), and a second memory die having a plurality of memory arrays disposed on the first memory die, the second memory die including a plurality of vias, wherein the plurality of vias are configured to allow the plurality of TWI to pass through the second memory die. The second memory die may be coupled to a second plurality of TWI. In this way, the interface chip may be used to communicatively couple the first memory die and the second memory die using the first and second plurality of TWI. Other apparatus, systems, and methods are included.
申请公布号 US7623365(B2) 申请公布日期 2009.11.24
申请号 US20070847113 申请日期 2007.08.29
申请人 MICRON TECHNOLOGY, INC. 发明人 JEDDELOH JOE M.
分类号 G11C5/06 主分类号 G11C5/06
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