Parallel bit test circuit and method for semiconductor memory device

摘要

A semiconductor memory device performs a parallel bit test on a plurality of memory blocks by writing test pattern data into the plurality of memory blocks, outputting two bits from each memory block in parallel and comparing the two bits output from each memory block with each other in a first test mode, and outputting two bits from respectively different memory blocks and comparing the two bits output from the respectively different memory blocks with each other in a second test mode.