发明名称 Switched capacitor circuit capable of minimizing clock feedthrough effect and having low phase noise and method thereof
摘要 A switched capacitor circuit includes a positive side capacitor coupled to a first positive side node; a first positive side switch element for selectively coupling the first positive side node to a second node according to a first control signal; and a precharge circuit coupled to the first positive side node for precharging the first positive side node to a precharge voltage for a predetermined time when the first positive side switch element is switched off according to the first control signal, and then for charging the first positive side node to a charge voltage until the first positive side switch element is switched on according to the first control signal. By rapidly precharging the first positive side node, the clock feedthrough effect is eliminated and the locking period of the VCO is shortened. Afterwards by charging the first positive side node, the phase noise of the VCO is minimized.
申请公布号 US7622980(B2) 申请公布日期 2009.11.24
申请号 US20060469875 申请日期 2006.09.03
申请人 MEDIATEK INC. 发明人 YEH EN-HSIANG
分类号 G06F7/64;H03L7/08;H03L7/099 主分类号 G06F7/64
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