| 摘要 |
One embodiment of the present invention provides a processor that is configured to execute load-swapped-partial instructions. An instruction fetch unit within the processor is configured to fetch the load-swapped-partial instruction to be executed. Note that the load-swapped-partial instruction specifies a source address in a memory, which is possibly an unaligned address. Furthermore, an execution unit within the processor is configured to execute the load-swapped-partial instruction. This involves loading a partial-vector-sized datum from a naturally-aligned memory region encompassing the source address. While loading the partial-vector-sized datum, bytes of the partial-vector-sized datum are rotated to cause the byte at the specified source address to reside at the least-significant byte position within the partial-vector-sized datum for a little-endian memory transaction, or to cause the byte to be positioned at the most-significant byte position within the partial-vector-sized datum for a big-endian memory transaction.
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