| 摘要 |
FIELD: information technologies. ^ SUBSTANCE: invention is related to computer engineering and may be used in building neuronet information processing systems. Device comprises parallel bus connected to units of data input and output, units of result memory stack, related to units of local data memory, local memory of data availability, local memory of commands, local memory of functional parametres, ring-bus circuit, with which operational units are related, as well as units of local data memory, local memory of commands, local memory of functional parametres, local memory of data availability and vacant register, local stacks of data packets, which are connected to according operational units, parallel bus, register of availability and with priority circuit with cyclic assignment of priorities, which is connected by availability register and to units of result memory stack. ^ EFFECT: improved efficiency of device due to data packet buffering and provision of equiprobable servicing of data packet stacks with the help of mechanism for cyclic assignment of priorities. ^ 2 cl, 2 dwg |
