METHOD OF COMPENSATING JITTERS DUE TO POWER SUPPLY VARIATION AND DIGITALLY CONTROLLED OSCILLATOR IMPLEMENTED THEREOF

摘要

The present invention constitutes a pseudo-differential pair and constitutes latch in a PMOS and NMOS to symmetrically compensate for the fluctuation in power supply on both rising and falling edge sides, thereby minimizing propagation delay jitter. The present invention has two nodes on both sides of a delay line for a coarse tuning and constitutes a block for a fine tuning, thereby providing a method for compensating for strength of a feedback latch of a delay cell corresponding to the fluctuation in power supply. The present invention increases driving force of the PMOS, when VDD is increased, and then the output voltage is increased to that extent so that the increased output voltage allows the NMOS latch to be strongly closed to generate a time delay to that extent in inverting a previous state, making it possible to make the entire propagation delay to be constant. As a result, even though the power supply is slightly fluctuated, a clock having a predetermined frequency can be oscillated without jitter noise