| 摘要 |
<p>A switched-capacitor decimator that can attenuate undesired signal components at odd harmonics of an output sample rate is described. In one design, the switched-capacitor decimator includes at least one sampling capacitor and multiple switches. For each sampling capacitor, the top plate is charged with a first input signal when the capacitor is selected for top charging, and the bottom plate is charged with a second input signal when the capacitor is selected for bottom charging. For each sampling capacitor, the top plate provides its stored charges to a first output signal and the bottom plate provides its stored charges to a second output signal when the capacitor is selected for reading. The switches couple the at least one sampling capacitor to the first and second input signals for charging and to the first and second output signals for reading.</p> |
