| 摘要 |
PROBLEM TO BE SOLVED: To provide a logic circuit detecting a degeneration one fault, a transition delay fault, a latch operation fault, etc. while suppressing increases in the number of test patterns. SOLUTION: The logic circuit includes a gated clock buffer which is set in a first state or a second state according to input signals to a control terminal for outputting input clock signals as output signals in the first state and fixing output signals to a specified value in the second state. The logic circuit also includes: a plurality of scan flip-flops including a flip-flop for receiving output signals for the gated clock buffer and constituting a scan chain. Signals for controlling input to the control terminal of the gated clock buffer are changed over between a first signal and a second signal. The first signal takes an enable value at all times during a test using the scan chain, and the second signal takes an enable value at a scan shift and takes a disable value during at least part of a period during capturing. COPYRIGHT: (C)2010,JPO&INPIT
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