| 摘要 |
<P>PROBLEM TO BE SOLVED: To solve a problem that a standard cell type CMOS semiconductor integrated circuit increases in layout area since wiring resources of upper-layer wiring are consumed even for a wiring connection between logic gate cells at near positions and then the logic gate cells do not have larger spread density because of deficiency of the wiring resources. Ž<P>SOLUTION: A logic gate cell includes a special terminal structure and then when logic gate cells are arranged at specified near positions, a wiring connection is made using only first and second metal wiring layers to increase wiring re sources of an upper layer, thereby reducing the layout area. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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