发明名称 |
Memory interface circuit and memory system including the same |
摘要 |
The memory interface circuit may include a master delay unit and a slave delay unit. The master delay unit generates a control signal for controlling a delay time based on a clock signal. The slave delay unit selects one signal of an inversion signal of the clock signal and a data strobe signal in response to a mode signal and delays the selected signal in response to the control signal. The slave delay unit selectively outputs a delayed clock signal that may be delayed by a first phase with respect to the clock signal or a delayed data strobe signal that may be delayed by a second phase with respect to the data strobe signal.
|
申请公布号 |
US2009285042(A1) |
申请公布日期 |
2009.11.19 |
申请号 |
US20090453523 |
申请日期 |
2009.05.14 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
CHAE KWAN-YEOB |
分类号 |
G11C7/00;G11C8/00 |
主分类号 |
G11C7/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|