| 摘要 |
A semiconductor memory device including a cyclic redundancy coding device is provided to reduce the number of logic and the number of line wiring by performing a logic assembly through several steps. A first pre-test signal generating part(120) outputs a plurality of bit data delivered through a first global line, a second global line, and a third global line as pre-test signals. A second pre-test signal generating part(140) outputs a plurality of bit data delivered through a fourth global line, a fifth global line, and a sixth global line as the pre-test signals. A third pre-test signal generating part(160) outputs a plurality of bit data delivered through a seventh global line, a eighth global line, and a data inversion line as the pre-test signals. A first test signal generating part(220) receives a plurality of pre-test signals of the first pre-test signal generating part and the second pre-test signal generating part, and outputs a plurality of test signals. A second test signal generating part(240) receives a plurality of pre-test signals of the third pre-test signal generating part and a ground voltage, and outputs a plurality of test signals. A cyclic redundancy test signal generating part(300) receives a plurality of test signals of the first test signal generating part and the second test signal generating part, and outputs a cyclic redundancy test signal of a plurality of bits. |
