MULTIPLEXER

摘要

A multiplexer includes an encoder (4). The encoder (4) includes: flip-flop circuits (4a, 4b) that output two signals having a transmission rate of B/2 at a frequency of B/2, while holding signals of each signal; an adder (4f) that adds the respective signals output from the flip-flop circuits (4a, 4b) and outputs the added signal; and a delay unit (4e) that delays the signal output from the flip-flop circuit (4b) by the time of 1/B, with respect to the signal output from the flip-flop circuit (4a), and outputs the signal delayed to the adder (4f).