| 摘要 |
A semiconductor integrated circuit comprising a plurality of memory circuits; a BSIT circuit 140 operable to output test vectors; and one or more register circuit(s) 150 each allocated on a signal line that transmits test vectors output by the BIST circuit 140 to any of the memory circuits, and operable to sequentially transfer the test vectors to an adjoining macro cell in accordance with the clock signals.
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