发明名称 Shallow trench isolation structure with low trench parasitic capacitance
摘要 Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.
申请公布号 US7619294(B1) 申请公布日期 2009.11.17
申请号 US20050262173 申请日期 2005.10.28
申请人 LSI CORPORATION 发明人 GOPINATH VENKATESH P.;KAMATH ARVIND;MIRABEDINI MOHAMMAD R.;LEE MING-YI
分类号 H01L21/76 主分类号 H01L21/76
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