发明名称 |
Techniques for mitigating, detecting, and correcting single event upset effects |
摘要 |
SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array. Correction techniques include reconfiguration of partial configuration data and "scrubbing" based on anticipated SEUs.
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申请公布号 |
US7620883(B1) |
申请公布日期 |
2009.11.17 |
申请号 |
US20060388897 |
申请日期 |
2006.03.24 |
申请人 |
XILINX, INC. |
发明人 |
CARMICHAEL CARL H.;BRINKLEY, JR. PHIL EDWARD |
分类号 |
G06F11/00;G01R31/28 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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