| 摘要 |
A memory device according to embodiments includes a cell array region. The cell array region comprises a plurality of transistors sharing a word line, a plurality of memory elements, and a plurality of first contacts configured to connect the plurality of transistors with the plurality of memory elements, respectively, and aligned with a pitch. The memory device further comprises a second contact positioned at the pitch, along an extension of a row of the plurality of first contacts, outside the cell array region, and configured to be in contact with the word line. |
| 主权项 |
1. A memory device comprising:
a cell array region comprising:
a plurality of transistors comprising a plurality of source/drain regions, the plurality of transistors sharing a word line among a plurality of word lines, the word lines having an embedded gate structure and extending from the cell array region to outside of the cell array region,a first insulating film on the word lines,a plurality of memory elements, anda plurality of first contacts configured to connect the plurality of transistors with the plurality of memory elements, respectively, and aligned with a pitch, the plurality of first contacts being in contact with the first insulating film and the plurality of source/drain regions; and a plurality of second contacts which are aligned with the same pitch as the pitch of the plurality of first contacts, and are positioned along respective extensions of rows of the plurality of first contacts, outside the cell array region, and configured to be in contact with the respective word lines, wherein a part of a lower surface of the respective second contacts is in contact with the corresponding word line. |
