Semiconductor memory device and data write method thereof

摘要

A semiconductor memory device includes a control circuit. The control circuit executes control to perform a verify operation with respect to only a lowest threshold voltage level of a memory cell at a time of a data write operation, and to skip the verify operation with respect to the other threshold voltage levels. The control circuit determines whether a verify pass bit number of the lowest threshold voltage level, which is counted by a bit scan circuit, is a prescribed bit number or more, and the control circuit further executes control, if the verify pass bit number is the prescribed bit number or more, to perform the verify operation with respect to only the lowest threshold voltage level and a threshold voltage level that is higher than the lowest threshold voltage level, and to skip the verify operation with respect to the other threshold voltage levels.

主权项

1. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells being capable of storing multi-level data; and a control circuit configured to perform a program cycle including a plurality of program loops, each of the program loops involving a first operation supplying a program voltage and a second operation supplying a verify voltage to a gate of a selected memory cell, the program cycle involving a first phase and a second phase, the control circuit being configured to perform a first program loop of the first phase, a second program loop of the first phase, and a third program loop of the second phase in order, the control circuit being configured to perform the second operation after performing the first operation in each of the program loops, the control circuit being configured to supply a first verify voltage in the second operations of both the first program loop and the second program loop, the control circuit being configured to supply the first verify voltage, and supply a second verify voltage in order without reducing a voltage of the gate of the selected memory cell to zero voltage after supplying the first verify voltage in the second operation of the third program loop, the second verify voltage being higher than the first verify voltage.