发明名称 Circuit technique to prevent device overstress
摘要 Techniques and circuits for ensuring one or more circuit components are not subjected to voltage levels above their rated voltage tolerance due to core logic and I/O logic supply voltages reaching final voltage levels at different times are provided. According to some embodiments, an internal voltage supply sense circuit may monitor a level of a voltage supply that powers core logic that generates control signals used to program a voltage regulator. In response to determining the core logic voltage supply is below a predetermined level, the sense circuit may generate one or more regulated voltage signals to override regulated voltage signals generated by the voltage regulator.
申请公布号 US7619444(B1) 申请公布日期 2009.11.17
申请号 US20050299080 申请日期 2005.12.08
申请人 NVIDIA CORPORATION 发明人 SHAIKH ASHFAQ R.;HONG CHANG HEE;KU TING-SHENG
分类号 H03K19/0175;H03K19/094 主分类号 H03K19/0175
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