发明名称 COMPILER AND CODE GENERATION METHOD THEREOF
摘要 PROBLEM TO BE SOLVED: To provide a method for generating an SIMD (single-instruction-multiple-data) creation code without a fraction portion by executing SIMD creation conversion wherein an outer loop is considered when a target data string by a conventional SIMD creation system is a part of a long continuous data string astride the outer loop because SIMD creation is not applied to the fraction portion when a data length is not divisible by SIMD parallelism when the data length of a range that is a target of SIMD optimization is short. SOLUTION: This compiler analyzes a target loop, analyzes an inner data length and the SIMD parallelism, thereafter obtains a loop expansion number of the outer loop surrounding an internal data part, and performs loop expansion and SIMD code conversion to the loop after the expansion. The compiler calculates a value (called a fraction) of the remainder when dividing the inner data length by the SIMD parallelism, and uses a value obtained by dividing a common multiple of the SIMD parallelism and the fraction by the fraction as the expansion number. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2009265708(A) 申请公布日期 2009.11.12
申请号 JP20080110835 申请日期 2008.04.22
申请人 HITACHI LTD 发明人 MOTOKAWA KEIKO
分类号 G06F9/45 主分类号 G06F9/45
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