Delta-sigma analog-to-digital converter with error suppression

摘要

A delta-sigma analog-to-digital converter (ΔΣ ADC) has a delta-sigma modulator, a decimation filter and an error suppression circuit. The delta-sigma modulator receives an analog input, and converts the analog input into a first digital output. The decimation filter is coupled to the delta-sigma modulator, and generates a second digital output according to the first digital output. The error suppression circuit is coupled to the decimation filter, and receives an error input and injects an error output into the second digital output according to the error input.

主权项

1. A delta-sigma analog-to-digital converter, comprising:
a delta-sigma modulator, arranged for receiving an analog input and converting the analog input into a first digital output; a first decimation filter, coupled to the delta-sigma modulator, the first decimation filter arranged for generating a second digital output according to the first digital output; and an error suppression circuit, coupled to the first decimation filter, the error suppression circuit arranged for receiving an error input and injecting an error output into the second digital output according to the error input; wherein the error suppression circuit receives the error input resulting from a digital-to-analog converter (DAC) of the delta-sigma modulator, the error input comprising an inter-symbol interference (ISI) error or an error resulting from clock jitter.