TESTING AND ALERT DEVICE AND METHOD FOR POWER LEAKAGES

摘要

A testing and alert device for power leakages of a computer includes a basic input/output system (BIOS) chip located on a motherboard of the computer, a south bridge chip connected to the BIOS chip, and an alarm device controlled by the BIOS chip. The south bridge chip has a first general purpose input/output terminal capable of being coupled to a ground of an exterior power source. The BIOS chip is capable of detecting the input signal of the first general purpose input/output terminal of the south bridge chip and outputting an alarm command to initiate the alarming device when the input signal from the first general purpose input/output terminal is at a high level.