发明名称 |
DELAYED DECISION FEEDBACK SEQUENCE ESTIMATOR AND METHOD |
摘要 |
PROBLEM TO BE SOLVED: To provide a delayed decision feedback sequence estimator (DDFSE) for increasing processing speed without relying on processing speed of a DDFSE computing unit. SOLUTION: The delayed decision feedback sequence estimator (DDFSE), whose received data symbol sequence is divided into a plurality of blocks of the same length mutually, includes a group of DDFSE computing units 104 equal in number to a length of each block. The group of DDFSE computing units are connected in a pipeline configuration and includes: a delayed decision feedback sequence estimator main unit 101 to execute delayed decision feedback sequence estimation of the blocks in parallel; and an edge effect detection and correction circuit 102 that detects an edge effect due to processing the delayed decision feedback sequence estimation of the separated block and corrects a relevant bit error. COPYRIGHT: (C)2010,JPO&INPIT |
申请公布号 |
JP2009268107(A) |
申请公布日期 |
2009.11.12 |
申请号 |
JP20090109534 |
申请日期 |
2009.04.28 |
申请人 |
NEC ELECTRONICS CORP;BOARD OF TRUSTEES OF LELAND STANFORD JR UNIV |
发明人 |
KAWASHIMA TOSHITSUGU;HOROWITZ MARK |
分类号 |
H04B3/06;H03M13/39;H04L1/00 |
主分类号 |
H04B3/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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