发明名称 MEMORY CONTROL SYSTEM
摘要 PROBLEM TO BE SOLVED: To perform a reading operation and operation monitoring of a two-port memory without affecting each other. SOLUTION: A two-port memory 6 is composed of a two-port SRAM with the same configuration as that of a two-port SRAM constituting a two-port memory 3 in a FIFO memory 2. A write address WAdd, write data WD, a write enable signal WE and an operation clock used in the two-port memory 3 are supplied to the two-port memory 6. Thus, the same write data WD are written in the two-port memories 3 and 6 at the same address and at the same time. In the two-port memory 3, read data RD is read from a read address Add given by a read pointer 5. On the other hand, in the two-port memory 6, read data RD is read from an address Add given from a CPU 7. Consequently, the two-port memory 6 can read the read data from an address different from that of the two-port memory 3 and at timing different from that of the two-port memory 3. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2009266176(A) 申请公布日期 2009.11.12
申请号 JP20080118525 申请日期 2008.04.30
申请人 DIGITAL ELECTRONICS CORP 发明人 MAEKAWA TOSHIYUKI
分类号 G06F12/16;G06F12/00 主分类号 G06F12/16
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