EMBEDDED CHIP SCALE PACKAGE AND MANUFACTURING METHOD THEREOF

摘要

PURPOSE: An embedded chip scale package and a manufacturing method thereof are provided to reduce a size of the semiconductor device by forming a via hole in a semiconductor die and installing a passive element inside the via hole. CONSTITUTION: In an embedded chip scale package and a manufacturing method thereof, at least one bond pad(111) is formed on a semiconductor die(110). At least via hole(112) is formed through an upper side and a lower-part of the semiconductor die. A first interconnection pattern(120) is formed in the via hole of the semiconductor die. The passive element(140) is electrically connected to the first interconnection pattern. A second wiring pattern(170) electrically connects the bond pad and the first interconnection pattern of the semiconductor die. A solder ball(190) is connected to the second wiring patterns.