发明名称 METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING BACK-END-OF-THE-LINE INTERCONNECT STRUCTURES
摘要 Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes selectively depositing a metal layer overlying a metal line of a metallization layer that is disposed in an ILD layer of dielectric material while an upper surface of the ILD layer that is laterally adjacent to the metal line is exposed. A hard mask layer is formed overlying the upper surface of the ILD layer laterally adjacent to the metal layer. The metal layer is removed to expose the metal line while leaving the hard mask layer intact. An interconnect is formed with the metal line adjacent to the hard mask layer.
申请公布号 US2016218034(A1) 申请公布日期 2016.07.28
申请号 US201514729342 申请日期 2015.06.03
申请人 GLOBALFOUNDRIES, Inc. 发明人 Zhang Xunyuan
分类号 H01L21/768;H01L21/306 主分类号 H01L21/768
代理机构 代理人
主权项 1. A method for fabricating an integrated circuit, the method comprising: selectively depositing a metal layer overlying a metal line of a metallization layer that is disposed in an ILD layer of dielectric material while an upper surface of the ILD layer that is laterally adjacent to the metal line is exposed; forming a hard mask layer overlying the upper surface of the ILD layer laterally adjacent to the metal layer; removing the metal layer to expose the metal line while leaving the hard mask layer intact; and forming an interconnect with the metal line adjacent to the hard mask layer.
地址 Grand Cayman KY