| 摘要 |
<P>PROBLEM TO BE SOLVED: To avoid primary system stop by PCI bus error processing on the primary side. Ž<P>SOLUTION: In a bridge circuit between the respectively independently operated systems of the primary side and the secondary side, reset control is executed so as not to be the protocol violation of a PCI bus of the primary side regardless of the timing of reset to the secondary side. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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