发明名称 DELAY LOCKED LOOP CIRCUIT AND DELAY LOCK METHOD
摘要 PURPOSE: A delay locked loop circuit and a delay locked method capable of re-locking and locking speed are provided to perform locking and re-locking operation and minimize noise and jitter by using a control method of a delay line. CONSTITUTION: A delay locked loop circuit and a delay locked method capable of re-locking and locking speed includes a phase detector(200), a code generator(300), and a controlling current delay line. The phase detector outputs the phase difference sensing signal and detects the phase difference of the reference clock and feedback clock. The code generator outputs digital code according to the phase difference sensing signal.
申请公布号 KR20090117118(A) 申请公布日期 2009.11.12
申请号 KR20080043023 申请日期 2008.05.08
申请人 HYNIX SEMICONDUCTOR INC. 发明人 KIM, YONG JU;HAN, SUNG WOO;SONG, HEE WOONG;OH, IC SU;KIM, HYUNG SOO;HWANG, TAE JIN;CHOI, HAE RANG;LEE, JI WANG;JANG, JAE MIN;PARK, CHANG KUN
分类号 G11C8/00;G11C5/14;G11C7/10 主分类号 G11C8/00
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