| 摘要 |
<p>A system for activating and deactivating a hardware device and comprising a first stage electronic deactivation unit operative, responsive to a deactivation request, to perform a first deactivation operation comprising deactivation of a first portion of the hardware device having low wake-up latency at a first time t1; ; and a second stage electronic deactivation unit including a breaking distance timer activated subsequently to the deactivation request thereby to time a breaking distance t2-t1, the second stage electronic deactivation unit being operative to deactivate a second portion of the hardware device having high wake-up latency at a subsequent second time separated from the first time t1 by t2 - t1, a power management system managing the supply of power to the hardware device, the power management system comprising at least one power source, at least one power supply regulator operative to control the supply of power from the power source to the hardware device in accordance with a selectable one of a plurality of regulator settings, and a hardware setting selector operative to select one of the plurality of regulator settings.; The first stage electronic deactivation unit is operative, responsive to a wake-up event, to reactivate the first portion of the hardware device. The second stage electronic deactivation unit is operative, responsive to the wake-up event, to deactivate the breaking distance timer. The hardware device comprises hardware components including a clock source and a PMU (power management unit). The system also preferably comprises a hardware power manager operative to receive an indication of the breaking distance, to receive an indication of the operating states of at least some of the hardware components of the hardware device and to determine accordingly, in hardware, activation/deactivation of at least one of the hardware device's clock source and PMU.</p> |
