发明名称 |
Electrostatic discharge device verification in an integrated circuit |
摘要 |
Processor-implemented techniques for verifying ESD device connectivity in an IC include the steps of: receiving an input dataset including layout parameters corresponding to the integrated circuit; identifying ESD devices based at least in part on the input dataset; extracting devices and parasitic elements in at least a portion of the integrated circuit based at least in part on the input dataset; generating a file including connectivity information and dimensional characteristics for extracted devices and parasitic elements associated with at least the identified ESD devices in the integrated circuit; identifying at least one ESD test based on the identified ESD devices and on connectivity to the identified ESD devices; and performing a linear network analysis for each identified ESD test based at least in part on the file.
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申请公布号 |
US7617467(B2) |
申请公布日期 |
2009.11.10 |
申请号 |
US20060610825 |
申请日期 |
2006.12.14 |
申请人 |
AGERE SYSTEMS INC. |
发明人 |
BELL DAVID AVERILL;LEUNG CHE CHOI;WROGE DANIEL MARK |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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