发明名称 |
Method for reducing charge loss in analog floating gate cell |
摘要 |
A voltage reference circuit provides a reference voltage in response to a programmed threshold voltage of a first non-volatile memory (NVM) transistor. The threshold voltage of the first NVM transistor is programmed by applying a programming voltage to commonly connected source/drain regions of a tunneling capacitor, which shares a floating gate with the first NVM transistor. During normal operation of the voltage reference circuit, the source/drain regions of the tunneling capacitor are connected to a second NVM transistor that has the same electrical and thermal characteristics as the floating gate of the first NVM transistor. As a result, charge loss from the floating gate of the first NVM transistor is advantageously minimized.
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申请公布号 |
US7616501(B2) |
申请公布日期 |
2009.11.10 |
申请号 |
US20070943578 |
申请日期 |
2007.11.20 |
申请人 |
SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C. |
发明人 |
SPOREA RADU A.;GEORGESCU SORIN S.;POENARU ILIE MARIAN I. |
分类号 |
G11C16/04 |
主分类号 |
G11C16/04 |
代理机构 |
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地址 |
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