| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To solve the matter of a bus type clock distribution circuit that a factor of switching error or jitter is inherent to the circuit because a reflected waveform from each branch line is superimposed on a drive waveform, and thereby the distributable distance and the number of fan-out are retrained severely when it is applied to a high frequency circuit. <P>SOLUTION: A clock distribution circuit which supplies an input or a generated clock signal to a sequential circuit via a plurality of stages of buffer includes a first transmission path (transmission path 4) which connects the output of buffer, of one or more of a plurality of stages, or the output of a generation circuit with the inputs of a plurality of buffers on the next stage in the manner of drawing an image with a single stroke of the brush, wherein the first transmission path includes a wiring path and a via group which connects upper metal wiring and lower metal wiring with an obtuse angle. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
