| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To make it possible to secure a holding margin while suppressing current consumption during low power consumption. <P>SOLUTION: A MOS transistor TrR has the same layout structure (L) as NMOS transistors Tn1, Tn2 which constitute a memory cell M, and stabilizes the voltage of a node N7 which is the reduced threshold voltage Vt of the MOS transistor TrR and impresses it to a node N2, while decreasing the both end voltages of a resistor R1 as holding margin voltages from the impressed voltage of the node N1 during the low power consumption. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
