| 摘要 |
An iterative low-density parity-check (LDPC) decoding system comprises a first shift register for storing bit estimates, a plurality of parity-check processing node banks configured for processing the bit estimates for generating messages, combiners configured for combining the messages with the bit estimates for generating updated bit estimates, and fixed permuters for permuting the updated bit estimates to facilitate storage and access of the bit estimates. A second shift register is provided for storing the messages, and a subtraction module subtracts messages generated a predetermined number of cycles earlier from the updated bit estimates.
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