| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a nonvolatile memory easy to manufacture in standard CMOSIC manufacturing processes and convenient to be used to adjust integrated circuits. <P>SOLUTION: This nonvolatile memory has an NMOS transistor Tr1 having a floating gate FG, NMOS transistors Tr2, Tr3 connected to the drain and source of this first NMOS transistor Tr1, and a PMOS transistor Tr4 and a PMOS transistor Tr5 using the floating gate FG as their gates. A read signal RD is inputted to the gates of the NMOS transistors Tr2, Tr3. A control gate signal CG is inputted to the source and n-well of the PMOS transistor Tr4. An erasing signal ER is inputted to the source and n-well of the PMOS transistor Tr5. A write data signal W-Data is inputted to the source of the NMOS transistor Tr1. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
