| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce an influence of an upper layer metal wiring pitch for pile driving to a pitch of gate wiring of a selection transistor included in a memory cell. Ž<P>SOLUTION: Word line drive circuits (2R, 2L) are arranged face to face on both sides of a memory cell array (1) and word line drivers are alternately arranged to memory cell lines in each word line drive circuit. The gate wirings (PGo, PGe) of the selection transistors of the memory cells are arranged corresponding to each memory cell line. The upper layer metal wirings (MLo, MLe) for pile driving are extended from the word line drive circuits to be arranged face to face to a connection area (10) at the center part of the memory cell array, and mutually and electrically connected to the gate wirings in the connection area. Metal wirings are arranged face to face at a pitch of twice of the gate wiring. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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