发明名称 MULTILINE SYSTEM AND ITS PERIPHERAL BOARD
摘要 <p><P>PROBLEM TO BE SOLVED: To enable line recognition in failure notification, etc., even using a CPU which can not memorize system setting. <P>SOLUTION: In case that a peripheral board 10 is, for example, in line B, a short circuit connector 20 is connected to a connector 14, and in case that it is in line A, the short circuit connector 20 is not connected. In the case of connecting the short circuit connector 20, CPU 11 recognizes that itself is in the line B by the output signal 3 of a photocoupler 12 becoming L. Moreover, for a failure determining circuit 4 within the CPU 11, both the outputs of its AND circuits 41 and 42 are L since the output signal 2 of the photocoupler 13 is L at normality. When the signal 2 becomes H due to occurrence of failure, only the output of the AND circuit 41 becomes H, and therefore CPU 31 in a UPS body 30 can recognize the occurrence of failure in the line B. <P>COPYRIGHT: (C)2010,JPO&INPIT</p>
申请公布号 JP2009261047(A) 申请公布日期 2009.11.05
申请号 JP20080103872 申请日期 2008.04.11
申请人 FUJI ELECTRIC SYSTEMS CO LTD 发明人 KISHI TOSHIHIRO;KOBAYASHI HISASHI
分类号 H02J9/06;H02J9/00 主分类号 H02J9/06
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