发明名称 DIGITAL LOGIC CIRCUIT, SHIFT REGISTER AND ACTIVE MATRIX DEVICE
摘要 <p>A digital logic circuit comprises a plurality of transistors of a same conduction type. A first transistor (40) has a source, gate and drain connected to a first circuit node (QB), a second circuit node (Y) and a first power supply line (Vdd), respectively. A second transistor (42) has a source, gate and drain connected to the second node (Y), the first node (QB) and the first supply line (Vdd), respectively. A third transistor (48) has a drain connected to the first node (QB). A fourth transistor (50) has a gate and drain connected to a third circuit node (Q) and the second circuit node (Y), respectively. A fifth transistor (52) has a gate and drain connected to the first and third nodes (QB, Q), respectively. Such a circuit may be used, for example, as a latch in a shift register of an active matrix addressing arrangement.</p>
申请公布号 WO2009133749(A1) 申请公布日期 2009.11.05
申请号 WO2009JP56919 申请日期 2009.03.27
申请人 SHARP KABUSHIKI KAISHA;ZEBEDEE, PATRICK;RAJENDRA, JAGANATH 发明人 ZEBEDEE, PATRICK;RAJENDRA, JAGANATH
分类号 H03K3/356;G09G3/20;G09G3/36 主分类号 H03K3/356
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