| 摘要 |
<P>PROBLEM TO BE SOLVED: To effectively utilize tag memories without enlarging the size of a cache memory when used as an SRAM (Static Random Access Memory) concerning a memory control circuit for effectively utilizing the tag memories constituting the cache memory. Ž<P>SOLUTION: The cache memory includes a plurality of sets of tag memories 37 and data memories 45. Based on the information of the control register 42 which selects whether the cache memory is used as the cache memory or the SRAM, a control circuit 35 divides data of a store register 32 for holding the 2N bytes of data to be written into L-bytes and M-bytes (L, M are integers being one or more, and L+M=2N) with respect to the two optional sets of tag memories 37. A control circuit 38 converts the L-bytes of data and M-bytes of data read from the two sets of optional tag memories 37 into the 2N bytes of data. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
|
