发明名称
摘要 <p>A process for fabricating an integrated circuit device is disclosed. The integrated circuit has a plurality of TFTs and an electrical interconnect structure. In the process, at least some constituents of the TFTs are formed on a first substrate. At least the interconnect structure is formed on a second substrate. The two substrates are laminated together to form the integrated circuit device having fully formed TFTs.</p>
申请公布号 JP4358430(B2) 申请公布日期 2009.11.04
申请号 JP20000372277 申请日期 2000.12.07
申请人 发明人
分类号 G02F1/136;H01L21/336;G02F1/1362;G02F1/1368;G09F9/30;H01L23/52;H01L27/12;H01L27/28;H01L29/786;H01L51/00;H01L51/05;H01L51/30;H01L51/40 主分类号 G02F1/136
代理机构 代理人
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