发明名称 Optimized memory addressing
摘要 Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.
申请公布号 US7612780(B2) 申请公布日期 2009.11.03
申请号 US20070784342 申请日期 2007.04.06
申请人 INTEL CORPORATION 发明人 FREKER DAVID E;SREENIVAS ADITYA;BOGIN ZOHAR;MUKKER ANOOP;TRIEU TUONG
分类号 G09G5/399;G06F12/00;G06F12/14;G06F13/00;G09G5/39 主分类号 G09G5/399
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