发明名称 |
Dual damascene patterning method |
摘要 |
A method for patterning a dual damascene structure in a semiconductor substrate is disclosed. The patterning is a metal hardmask based pattering eliminating at least resist poisoning and further avoiding or at least minimizing low-k damage. The method can be used as a full-via-first patterning method or a partial-via-first patterning method.
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申请公布号 |
US7611986(B2) |
申请公布日期 |
2009.11.03 |
申请号 |
US20060400852 |
申请日期 |
2006.04.10 |
申请人 |
IMEC |
发明人 |
OLMEN JAN VAN;HOVE MARLEEN VAN;STRUYF HERBERT;HENDRICKX DIRK;VANHAELEMEERSCH SERGE;BOULLART WERNER |
分类号 |
H01L21/4763 |
主分类号 |
H01L21/4763 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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